At present various reading circuits (so-called sense amplifiers) are known, for reading analog or multi-level threshold voltage of nonvolatile memory cells. Two embodiments are for example illustrated in FIGS. 2 and 5 of European patent application 96830612.6 of Dec. 5, 1996 in the name of the same applicant. According to these solutions, the drain (or source) terminal is connected to a current source, which sets the current flowing in the memory cell (bias current), as well as to the inverting input of an operational amplifier; the source (or drain) terminal is biased to a constant voltage; and the gate terminal is connected to the output of the operational amplifier, the non-inverting input of which receives a reference voltage with a predetermined value (for example it is connected to ground). The reading circuit thus forms a closed-loop circuit wherein the output voltage of the operational amplifier is the same as the gate-source voltage of the cell (optionally minus the reference voltage, which has a known value), wherein the cell overdrive (difference between the voltage applied between the source and drain terminals of the cell and its zero current threshold voltage) is constant, and is set by the current source. As a result, the output voltage of the operational amplifier is equal to the cell threshold voltage, measured at the set bias current.
In this known solution, when the drain terminal is connected to the operational amplifier, advantageously, the cell constant current threshold voltage is read directly and the gate voltage and thus the stresses of the gate region (gate stress) are minimized. On the other hand, it is disadvantageous for the gate voltage to be negative, since this requires generation of appropriate reference voltages, and there are increased difficulties in designing the operational amplifier; in addition, it is disadvantageous for the parasitic drain capacitance (which is approximately 2 pF) to be driven by the transconductance of the flash cell.
In the second solution the problem caused by the presence of a negative voltage at the drain terminal is avoided, however the high capacitance present at the source terminal of flash cells (approximately 1 nF) becomes sensible, and reading memory arrays with a high number of cells becomes slow.
A different solution is provided in European patent application no. 97830172.9 of Apr. 15, 1997 in the name of the same applicant, wherein the drain terminals of the cell to be read and of a reference cell are connected to the two output nodes of a current mirror circuit, and to respective inputs of an operational amplifier, and the output of the operational amplifier is connected to the gate terminal of the reference cell. Thereby a feedback loop comprising the reference cell is provided, and the output of the operational amplifier is linearly linked to the zero current threshold voltage of the cell to be read, minus the zero current threshold voltage of the reference cell and the gate voltage of the cell to be read.
Advantageously, this solution provides a very fast reading (0.3 .mu.s), since the increased parasitic capacitance (capacitance associated with the gate terminal of the array cell to be read) is excluded from the feedback loop, whereas the drain capacitance is driven by the transconductance (which is high) of an NMOS biasing transistor, forming a cascode structure. This solution also permits parallel reading of different cells of the array. A variant of this solution uses a MOS transistor as a reference element.
The disadvantage of this solution consists in the fact that reading is carried out indirectly, i.e., a reference device is needed, the features whereof are as constant as possible over a period of time, and with use. This condition is particularly critical if a memory cell is used as a reference. In addition, in this solution, the gate voltage of all the cells arranged on the line of the cell to be read must always be set to the maximum value, and thus the stress at the gate region of these cells is maximal.